In general, image sensors are semiconductor devices for converting an optical image into an electrical signal. In a charge coupled device (CCD), charge carriers are stored in and transferred to closely formed individual MOS capacitors
The CCD uses a complicated driving method and consumes a lot of power. A CCD has many disadvantages such as a large number of mask operations and inability to incorporate a signal processing circuit within a CCD chip such that it is difficult to integrate a CCD on a single chip. Therefore, a CMOS image sensor using a sub-micron CMOS manufacturing technology is under development in order to overcome these disadvantages.
CMOS image sensors are formed using CMOS technology and incorporate MOS transistors corresponding to each unit pixel, and a control circuit and a signal processing circuit as peripheral circuits, where a switching method is used for sequentially detecting outputs by employing the MOS transistors.
In general, a CMOS image sensor includes a photodiode (PD) and a MOS transistor within a unit pixel, and realizes an image by sequentially detecting signals using a switching method. Since a CMOS image sensor uses CMOS manufacturing technology, the CMOS image sensor has low power consumption, typically requires about 20 masks, and has a very simple manufacturing process compared to a CCD process, which requires about 30-40 masks. In addition, a variety of signal processing circuits within the CMOS image sensor can be realized in one-chip. Accordingly, the CMOS image sensor is in the limelight as the next generation image sensor and is widely used in a variety of applications such as digital still cameras (DSC), personal computer (PC) cameras, and mobile cameras.
CMOS images sensors are generally classified into 3T type CMOS image sensors, 4T type CMOS image sensors, or 5T type CMOS image sensors depending on the number of transistors formed in a unit pixel. The 3T type CMOS image sensor includes one PD and three transistors. The 4T type CMOS image sensor includes one PD and four transistors. A related art CMOS image sensor will be described with reference to the accompanying drawings.
FIG. 1 is an equivalent circuit diagram of a general 4T type CMOS image sensor, and FIG. 2 is a lay-out diagram illustrating a unit pixel of a general 4T type CMOS image sensor.
Referring to FIGS. 1 and 2, a unit pixel of the 4T type CMOS image sensor includes a photodiode (PD) 10 as a photo-electric converting part, and four transistors Tx, Rx, Dx, and Sx.
Here, the four transistors are a transmission transistor Tx 20, a reset transistor Rx 30, a drive transistor Dx 40, and a select transistor Sx 50. Also, a load transistor 65 is electrically connected to a drain terminal of the select transistor that serves as an output terminal for the unit pixel.
In the unit pixel of the related art 4T type CMOS image sensor illustrated in FIG. 2, an active region and a device isolation region are defined. The photodiode PD is formed at the wide portion of the active region, and gate electrodes 23, 33, 43 and 53 of the four transistors Tx, Rx, Dx, and Sx, respectively, are formed overlapping the narrow portion of the active region.
FIG. 3 is a lay-out diagram for describing a poly routing method of a CMOS image sensor according to the related art.
Referring to FIG. 3, gates of the respective transistors Tx, Rx, Dx, and Sx of the 4T type CMOS image sensor are formed in shapes of gate electrodes 23(a and b), 33(a and b), 43(a and b), and 53(a and b). Photodiodes (PD) 10a and 10b are formed in the substrate at one side of Tx gate electrodes 23a and 23b. N+ type well regions are formed on a surface of a portion of the semiconductor substrate that is located at both sides of the gate electrodes 23(a and b), 33(a and b), 43(a and b), and 53(a and b) to serve as source/drain regions for each transistor.
Also, a predetermined portion of an N+ type well region between the gate electrodes 23, 33, 43, and 53 of the each transistor is defined as a floating diffusion node (FD).
Where a PD of a CMOS image sensor changes into a salicide, a leakage characteristic remarkably deteriorates, and causes a great increase of dark current.
Therefore, to prevent a PD from changing into salicide, a plasma enhanced tetra ethyl ortho silicate (PE-TEOS)-based oxide layer, which is a salicide blocking layer, is deposited. Then, a non-salicide mask for etching the PE-TEOS layer is disposed around PDs 10a and 10b as illustrated by the dotted lines in FIG. 3.
At this point, since a salicide blocking oxide layer is removed primarily using wet etching, the non-salicide mask is disposed to have a margin around the PDs so as to secure a process margin.
In this case, the poly routing line of a pixel part partially remains as a non-salicide portion due to the non-salicide mask, and resistance of the poly routing line increases. When the resistance of the poly routing line increases, an RC delay is generated.
FIG. 4 is a lay-out diagram for illustrating another poly routing method of a CMOS image sensor according to the related art.
Referring to FIG. 4, not only a PD region but also a floating diffusion node (FD) in a unit pixel is prevented from being salicided in order to improve low illumination characteristic of a CMOS image sensor. Here, the space between the salicide blocking masks is narrow, making it difficult to use a current mid ultra violet (MUV) process, which results in a reduction in yield.
In addition, as shown in FIG. 4, a portion of a poly routing line also partially remains as a non-salicide portion due to the mask shown with a dotted line in FIG. 4.